The present invention relates to a two-step parallel analog to digital converter capable of realizing fast and highly accurate A/D conversion with a circuitry of a practical scale and more particularly to the prevention of any conversion error in its lower significant bits.
A typical example of the conventional high-speed A/D converters is the so-called flash type. With this type of A/D converter, the scale of its circuitry increases in an exponential function in proportion to an increase in the number of bits in a digital output. 0n the other hand, a two-step parallel A/D converter can realize a fast and highly accurate A/D convertion and an A/D converter having a relatively large number of output bits with a reasonable circuit scale and an example of this type is described in the Digest of Papers, International Conference on Consumer Electronics, June 8, 1984, pp. 150-151. In a conventional two-step parallel A/D converter shown in FIG. 9 of the accompanying drawings, a first flash type A/D converter including a comparator group 802, a latch circuit group 803, a binary encoder 804 and a latch circuit group 805 converts an analog input 801 to a digital signal and determines upper significant bits 816. On the other hand, a segment current-type D/A converter (hereinafter referred to as a DAC) 808 which receives the outputs of the latch circuit group 803 and including a resistor group 806 connected to these latch circuit outputs and a resistor 807 connected to the resistor group 806 reconverts the digital signal of the upper significant bits to an analog value. A subtracting circuit 810 determines the difference between the analog input delayed for a time corresponding to the time required for the conversion in the first A/D converter and the DAC by a delay circuit 809 and the D/A converted output and the difference is amplified by an amplifier 811. The result is subjected to A/D conversion by a second flash-type A/D converter including a comparator groups 812, a latch circuit group 813, a binary encoder 814 and a latch circuit group 815, thereby determining lower significant bits 817.
Thus, with the two-step parallel A/D converter, the conversion quantizing error of the first flash-type A/D converter is subjected to A/D conversion by the second flash type A/D converter. As a result, it is impossible to ensure the desired accuracy down to the lower significant bits unless the following two conditions are satisfied:
(a) An quantizing error is always obtained accurately. PA1 (b) The quantizing error obtained is accurately converted to a digital signal of the lower significant bits.
To satisfy the condition (a), there must be the equality between the full scale value of the output variation of the D/A converter for reconverting the digital output of the upper significant bits and the full scale value of the input applied to the first flash-type A/D converter. Otherwise, the subtractor output includes not only the quantizing error of the first flash-type A/D converter but also an offset varying in dependence on the voltage level of the input analog signal. On the other hand, to satisfy the condition (b) requires that the full scale value of the subtractor output corresponding to the quantizing error coincide with the input full scale range of the second flash-type A/D converter. In the example shown in FIG. 9, satisfying these conditions requires that not only the value of the output resistor 807 of the DAC 808 or the values of the individual (segment) resistors 806 are adjusted but also the gain of the subtracting amplifier 811 or the values of upper and lower reference voltages applied to the comparator group of the second flash-type A/D converter are adjusted. Particularly in the case of IC A/D converters, there are disadvantages that it is necessary to provide terminals for such adjusting purposes with the resulting increase in the number of the package pins, that the high speed performance is deteriorated by an increase in the parasitic capacitance due to the provision of a pin for detecting the output voltage of the DAC 808 and so on.